Pepper-computer Modular Computers RS485 Bedienungsanleitung PDF herunterladen (Seite 306)

SMART I/O User’s Manual

October 01, 1996

Page 6- 24

Chapter 6 Communications Modules

6.2.7.5 Compare Register

This 24-bit register indicates the comparison value and is cleared after a

power-on reset.

6.2.7.6 Identification Register

The identification register is read only and fixed at a value of $81.

6.2.7.7 Status Register

The 16-bit status register is divided into two sub-registers which are partly

cleared after a power-on reset and show:

• IP : Interrupt Pending flags • DF : Data Flow

• PE : Parity Error • ER1 : End-of-Range 1

• TC : Transmission Complete • ER2 : End-of-Range 2

• OL : Open Line • MH : Match

IP, PE, TC, OL, DF and MH flags are cleared after a reset. ER1 and ER2

represent the current hardware condition

6.2.7.8 STAT1 Register

IP0-PE interrupt pending on parity error

IP1-TC interrupt pending on transmission complete

IP2-ER1 interrupt pending on end-of-range switch 1

IP3-ER2 interrupt pending on end-of-range switch 2

IP4-MH interrupt pending on comparison match

DF SSI data flow (True/False)

OL open line (True/False)

ST1-7 ST1-6 ST1-5 ST1-4 ST1-3 ST1-2 ST1-1

OL unused DF IP4-MH IP3-ER2 IP2-ER1 IP1-TC

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Pepper-computer Modular Computers RS485 Bedienungsanleitung Seite 306